C8051F330_07 Datasheet, PDF (75/216 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F330/1/2/3/4/5
program memory space for non-volatile data storage. Refer to Section “11. Flash Memory” on page 105
for further details.
Mnemonic
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
DA A
ANL A, Rn
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, Rn
XRL A, direct
XRL A, @Ri
Table 9.1. CIP-51 Instruction Set Summary
Description
Bytes
Arithmetic Operations
Add register to A
1
Add direct byte to A
2
Add indirect RAM to A
1
Add immediate to A
2
Add register to A with carry
1
Add direct byte to A with carry
2
Add indirect RAM to A with carry
1
Add immediate to A with carry
2
Subtract register from A with borrow
1
Subtract direct byte from A with borrow
2
Subtract indirect RAM from A with borrow
1
Subtract immediate from A with borrow
2
Increment A
1
Increment register
1
Increment direct byte
2
Increment indirect RAM
1
Decrement A
1
Decrement register
1
Decrement direct byte
2
Decrement indirect RAM
1
Increment Data Pointer
1
Multiply A and B
1
Divide A by B
1
Decimal adjust A
1
Logical Operations
AND Register to A
1
AND direct byte to A
2
AND indirect RAM to A
1
AND immediate to A
2
AND A to direct byte
2
AND immediate to direct byte
3
OR Register to A
1
OR direct byte to A
2
OR indirect RAM to A
1
OR immediate to A
2
OR A to direct byte
2
OR immediate to direct byte
3
Exclusive-OR Register to A
1
Exclusive-OR direct byte to A
2
Exclusive-OR indirect RAM to A
1
Clock
Cycles
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
2
1
1
2
2
1
4
8
1
1
2
2
2
2
3
1
2
2
2
2
3
1
2
2
Rev. 1.5
75