C8051F330_07 Datasheet, PDF (7/216 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F330/1/2/3/4/5
List of Figures
1. System Overview
Figure 1.1. C8051F330 Block Diagram.................................................................... 19
Figure 1.2. C8051F331 Block Diagram.................................................................... 19
Figure 1.3. C8051F332 Block Diagram.................................................................... 20
Figure 1.4. C8051F333 Block Diagram.................................................................... 20
Figure 1.5. C8051F334 Block Diagram.................................................................... 21
Figure 1.6. C8051F335 Block Diagram.................................................................... 21
Figure 1.7. Comparison of Peak MCU Execution Speeds ....................................... 22
Figure 1.8. On-Chip Clock and Reset ...................................................................... 23
Figure 1.9. On-Board Memory Map ......................................................................... 24
Figure 1.10. Development/In-System Debug Diagram............................................. 25
Figure 1.11. Digital Crossbar Diagram ..................................................................... 26
Figure 1.12. PCA Block Diagram.............................................................................. 27
Figure 1.13. PCA Block Diagram.............................................................................. 27
Figure 1.14. 10-Bit ADC Block Diagram ................................................................... 28
Figure 1.15. Comparator0 Block Diagram ................................................................ 29
Figure 1.16. IDA0 Functional Block Diagram ........................................................... 30
2. Absolute Maximum Ratings
3. Global Electrical Characteristics
4. Pinout and Package Definitions
Figure 4.1. QFN-20 Pinout Diagram (Top View)...................................................... 37
Figure 4.2. QFN-20 Package Drawing..................................................................... 38
Figure 4.3. QFN-20 Solder Paste Recommendation ............................................... 39
Figure 4.4. Typical QFN-20 Landing Diagram ......................................................... 40
Figure 4.5. PDIP-20 Pinout Diagram (Top View) ..................................................... 41
Figure 4.6. PDIP-20 Package Drawing .................................................................... 42
5. 10-Bit ADC (ADC0, C8051F330/2/4 only)
Figure 5.1. ADC0 Functional Block Diagram ........................................................... 43
Figure 5.2. Typical Temperature Sensor Transfer Function .................................... 45
Figure 5.3. 10-Bit ADC Track and Conversion Example Timing.............................. 47
Figure 5.4. ADC0 Equivalent Input Circuits ............................................................. 48
Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data... 55
Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 55
Figure 5.7. ADC Window Compare Example: Right-Justified Differential Data ....... 56
Figure 5.8. ADC Window Compare Example: Left-Justified Differential Data ......... 56
6. 10-Bit Current Mode DAC (IDA0, C8051F330 only)
Figure 6.1. IDA0 Functional Block Diagram............................................................. 59
Figure 6.2. IDA0 Data Word Mapping...................................................................... 60
7. Voltage Reference (C8051F330/2/4 only)
Figure 7.1. Voltage Reference Functional Block Diagram ....................................... 63
8. Comparator0
Figure 8.1. Comparator0 Functional Block Diagram................................................ 67
Figure 8.2. Comparator Hysteresis Plot................................................................... 68
Rev. 1.5
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