C8051F330_07 Datasheet, PDF (133/216 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F330/1/2/3/4/5
SFR Definition 14.5. P0MDOUT: Port0 Output Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xA4
Bits7–0:
Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in regis-
ter P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
(Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless
of the value of P0MDOUT).
SFR Definition 14.6. P0SKIP: Port0 Skip
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xD4
Bits7–0:
P0SKIP[7:0]: Port0 Crossbar Skip Enable Bits.
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana-
log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil-
lator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
SFR Definition 14.7. P1: Port1
R/W
P1.7
Bit7
R/W
P1.6
Bit6
R/W
P1.5
Bit5
R/W
P1.4
Bit4
R/W
P1.3
Bit3
R/W
P1.2
Bit2
R/W
R/W
P1.1
P1.0
Bit1
Bit0
(bit addressable)
Reset Value
11111111
SFR Address:
0x90
Bits7–0:
P1.[7:0]
Write - Output appears on I/O pins per Crossbar Registers.
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0).
Read - Always reads ‘0’ if selected as analog input in register P1MDIN. Directly reads Port
pin when configured as digital input.
0: P1.n pin is logic low.
1: P1.n pin is logic high.
Rev. 1.5
133