SDA9361 Datasheet, PDF (8/47 Pages) Siemens Semiconductor Group – DDC-PLUS-Deflection Controller

SDA 9361
1.4 Pin Description (cont’d)
Pin No. Symbol Type
Description
28
VSYNC I/TTL
V-sync input
29
HD
Q
Control signal output for H driver stage
30
TEST
I/TTL
Switching normal operation (TEST = L) and test mode
(TEST = H: pins 7, 27, 31, 32, 33, 40, 44 are additional
test pins)
31
FH1_2 I/TTL
Switching between 1F_H mode (L) and 2F_H mode (H)
(Pin SELFH1_2 = 0)
32
CLEXT I/TTL
Switching between internal (L) and external clock (H)¹⁾
33
SELFH1_2 I/TTL
34
V_DD(A3)
S
35
HSYNC I
Selection of switching between 1F_H mode and 2F_H
mode
SELFH1_2 = 0:1F_H/2F_H selected via pin FH1_2
SELFH1_2 = 1:1F_H/2F_H selected via
Ι²C-Bus register 00_H, Bit D5
Analog supply
HSYNC input (CLEXT = 1: TTL; CLEXT = 0: analog)¹⁾
36
V_REFC
I
37
V_SS(A3)
S
38
V_DD(D)
S
39
V_SS(D)
S
40
SSD
I/TTL
Reference voltage for sync ADC
Analog ground
Digital supply
Digital ground
Disables softstart
41
V_SS(A4)
S
42
LF
IQ
Analog ground
PLL loop filter
43
V_DD(A4)
S
44
VOFFD I/TTL
Analog supply
Defines default value of VOFF-Bit
(Ι²C-Bus register 00_H, Bit D7)
1) _{The external clock mode can not be used with 33.75 kHz and 35 kHz line frequency.}
Semiconductor Group
8
1998-02-01