SDA9361 Datasheet, PDF (42/47 Pages) Siemens Semiconductor Group – DDC-PLUS-Deflection Controller

5.2 Timing Diagram of SCAN
SDA 9361
HSYNC
(odd field)
HSYNC
(even field)
2 _*FH
(internal)
123
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
123
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
d0
VSYNC
VBL
(BSE = 0)
1 Line
21 Lines
appr. 1 Line + d0
VD-
(SSE = 0)
Start of Scan
SCAN
(SSE = 0)
VD-
(SSE = 1,
start vert.
scan = 12)
SCAN
(SSE = 1,
start vert.
scan = 12)
appr. 8.5 Lines
appr. 0.5 Lines
appr. 11.5 Lines
Start of Scan
UED10281
Figure 9
Timing Diagram of SCAN if STE = 0
Semiconductor Group
42
1998-02-01