SDA9361 Datasheet, PDF (12/47 Pages) Siemens Semiconductor Group – DDC-PLUS-Deflection Controller

SDA 9361
2.2 Circuit Description
The HSYNC is reference for a numeric PLL. This PLL generates a clock which is phase
locked to the incoming horizontal sync pulse and exactly 864 times faster then the
horizontal frequency. In order to lock the internal frequency to the external sync signal
positive horizontal sync pulses are required (see figure 4).
t_r
t_W
V _HSmax
V _HSpp
V _HSmin
UED10279
Figure 4
Incoming Signal HSYNC (CLEXT = 0)
Pulse width t_w for Ι²C-Bus Bit ’HSWID’ = 0:
3 µs ... 6.1 µs low FH-range
1.5 µs ... 3.1 µs high FH-range
Pulse width t_w for Ι²C-Bus Bit ’HSWID’ = 1:
3 µs ... 8.8 µs low FH-range
1.5 µs ... 4.0 µs high FH-range
Rise time t_r:100 ns minimum (CLEXT = 0)
The described input signal is first applied to an A/D converter. Conversion takes place
with 6 Bits and a nominal frequency of 27 MHz. The digital PLL uses a low pass filter to
obtain defined slopes for further measurements (PAL/NTSC applications). In addition
the actual high and low level of the signal as well as a threshold value is evaluated and
used to calculate the phase error between internal clock and external horizontal sync
Semiconductor Group
12
1998-02-01