SDA9361 Datasheet, PDF (10/47 Pages) Siemens Semiconductor Group – DDC-PLUS-Deflection Controller

SDA 9361
2
System Description
2.1 Functional Description
The main input signals are HSYNC with standard or doubled horizontal frequency and
VSYNC with vertical frequencies of 50/100 Hz or 60/120 Hz.
The VSYNC is processed in a noise reduction circuit to enable synchronization by worse
transmission too.
The output signals control the horizontal as well as the vertical deflection stages and the
east/west raster correction circuit.
The H-output signal HD compensates the delays of the line output stage and its phase
can be modulated vertical frequent to remove horizontal distortions of vertical raster lines
(V-Bow, V-Angle). Time reference is the middle of the front and back edge of the line
flyback pulse. A positive HD pulse switches off the line output transistor. Maximal H-shift
is about 4.5 µs (for 1F_H) or 2.25 µs (for 2F_H).
Picture tubes with 4:3 or 16:9 aspect ratio can be used by adapting the raster to the
aspect ratio of the source signal.
The V-output saw-tooth signals VD- and VD+ controls a DC coupled output stage and
can be disabled. Suitable blanking signals are delivered by the IC.
The east/west output signal E/W is a vertical frequent parabola of 4th order, enabling an
additional corner correction, separately for the upper and lower part.
The pulse width modulated horizontal frequent output signal PWM is for optional use. It
can be modulated between 1 and 215 steps. The step width is 4_*t_H/864.
The output D/A delivers a variable DC signal for general purpose.
The picture width and picture height compensation (PW/PH Comp) processes the beam
current dependent input signal ABL with effect to the outputs E/W and VD to keep width
and height constant and independent of brightness.
The alignment parameter Horizontal Shift Compensation enables to adjust the influence
of the input signal ABL on the horizontal phase.
The selectable start up circuit controls the energy supply of the H-output stage during the
receiver's run up time by smooth decreasing the line output transistors switching
frequency down to the normal operating value (softstart). HD starts with about double the
line frequency and converges within 85 ms to its final value. The high time is kept
constant.The normal operating pulse ratio H/L is 45/55.
The protection circuit watches an EHT reference and the saw-tooth of the vertical output
stage. H-output stage is switched off if the EHT succeeds a defined threshold or if the
V-deflection fails (refer to page 46).
HPROT: Input
V_i < V2
V_i > V1
V2 ≤ V_i < V1
Continuous blanking
HD disabled
Operating range
Semiconductor Group
10
1998-02-01