SDA9361 Datasheet, PDF (19/47 Pages) Siemens Semiconductor Group – DDC-PLUS-Deflection Controller

SDA 9361
STDBY:
Stand-by mode
0: normal operation
1: stand-by mode (all internal clocks are disabled)
2FH:
BD:
Setting of line frequency
0: low range of line frequency (14900 Hz ... 17650 Hz)
1: high range of line frequency (29800 Hz ... 35300 Hz)
Note: this bit is don’t care if pin SELFH1_2 has L-level
Blanking disable
0: horizontal and vertical blanking enabled
1: horizontal and vertical blanking disabled
RABL:
ABL input range
0: 2 V ... 3 V
1: 0 V ... 4 V
VR1 ... VR0:
Reduction of the vertical size
00: 100 % V-size
(16:9 source on 16:9 display)
01: 75 % V-size
(16:9 source on 4:3 display)
10: 66 % V-size
(two 4:3 sources on 16:9 display)
11: 50 % V-size
(two 16:9 sources on 16:9 display)
HDE:
HD enable
0: line is switched off (HD disabled, that is L-level)
1: line is switched on (HD enabled)
Default value depends on pin 40 (SSD)
SSD = Low: 0
SSD = High: 1
The Deflection Control Byte 1 includes the following bits:
0
X
NSA
STE
GBE SRSE
SSE
BSE
NSA:
No self adaptation
0: self adaptation on
1: self adaptation off
Semiconductor Group
19
1998-02-01