SDA9361 Datasheet, PDF (44/47 Pages) Siemens Semiconductor Group – DDC-PLUS-Deflection Controller

5.3 Power On/Off Diagram
SDA 9361
Supply
Voltage
Power-
On-
Reset
X1, X2
HD
Ι²C Bus
32
Cycles
32
Cycles
Tristate
SSD = 0: ~ 250 µs¹⁾
SSD = 1: ~ 380 µs¹⁾
Ι²C Registers 01_H ...1C_H,1F _H
Programmable
Ready
Tri-
state
SSD = 0: ~ 250 µs¹⁾
SSD = 1: ~ 380 µs¹⁾
Ι²C Registers 01_H ...1C_H,1F _H
Programmable
Ready
Tristate
V_REFP,
V_REFH,
V_REFL
Protection
Active
Inactive
Ι²C Reg.
00_H, 1D_H, 1E_H,
De-
fault
Programmable
De-
fault
Programmable
De-
fault
44_H ...48 _H
Ι²C Reg.
01_H ...1C_H,1F_H
Default
Programmable
Default
Programmable
De-
fault
CLL
Active
CPU
Inactive
~ 42 Cycles
~ 42 Cycles
Power On
1) _{For low FH-range this time has to be multiplied by 2}
Glitch
Power Off
UED10283
Figure 11
Semiconductor Group
44
1998-02-01