SDA9361 Datasheet, PDF (23/47 Pages) Siemens Semiconductor Group – DDC-PLUS-Deflection Controller

SDA 9361
The Universal Register 1 (Subaddress 45_H) includes the following bit:
0
0
NOISY
0
0
0
0
0
VCR
NOISYVCR:
Handling of noisy input signals in VCR mode
0: normal handling
1: improved handling
Note: this bit is don’t care if bit VCR = 0 (TV mode)
The Universal Register 3 (Subaddress 47_H) includes the following bits:
0
0
0 KILL_ZIP TC_3RD
0
0
0
KILL_ZIP:
Top flutter suppression
0: no top flutter suppression
1: top flutter suppression
(phase jumps max. ±12 µs for low FH-range
rsp. max. ± 6 µs for high FH-range)
TC_3RD:
Third time constant
0: slow VCR time constant
1: fast VCR time constant
Note: this bit is don’t care if bit VCR = 0 (TV mode)
The Internal Voltage Ref. Control Byte includes the following bits:
BANDG4 BANDG3 BANDG2 BANDG1 BANDG0 BANDG BANDG4 0
OFF
OFF
BANDG4 ...
BANDG0:
Adjustment of internal bandgap reference
10000: Reference Output voltage min
:
01111: Reference Output voltage max
Typical adjustment range is 0.5 V.
BANDGOFF: Bandgap Off
0: V_REFH, V_REFL derived internally from V_REFP
Semiconductor Group
23
1998-02-01