SDA9361 Datasheet, PDF (45/47 Pages) Siemens Semiconductor Group – DDC-PLUS-Deflection Controller

5.4 Standby Mode, RESN Diagram
SDA 9361
Standby
RESN
HD
φ2-Loop
CPU
V_REFP,
V_REFH,
V_REFL
Protection
Active
Inactive
Active
Inactive
Active
Inactive
Free Run
φ2-Loop
~ 42 CLL Cycles
SSD = 0: ~ 250 µs¹⁾
SSD = 1: ~ 380 µs¹⁾
32 x 1
Cycles
Free
Run
~ 42 CLL Cycles
Ι²C Bus
Ready
Tristate
Ready
Ι²C Reg.
Programmable
01_H ...1C_H,1F_H
Ι²C Reg.
00_H, 1D_H, 1E_H
44_H ...48 _H
Default Values
Programmable
Programmable
Default Values
Programmable
Default
Values
Programmable
Standby Mode
1) _{For low FH-range this time has to be multiplied by 2}
External Reset
UED10284
Figure 12
Semiconductor Group
45
1998-02-01