SDA9361 Datasheet, PDF (36/47 Pages) Siemens Semiconductor Group – DDC-PLUS-Deflection Controller

SDA 9361
3.1 Recommended Operating Conditions (cont’d)
Parameter
Symbol
Limit Values Unit
min. nom. max.
Input CLKI (External Clock Generation, CLEXT = High)
Input frequency
f_I
12.5 13.5 15
25 27 30
MHz
MHz
Quartz Oscillator Input / Output X1, X2
Crystal frequency
24.576
MHz
Crystal resonant
impedance
External capacitance
40 Ω
27
pF
I²C Bus (All Values are Referred to min.(V_IH) and max.(V_IL)
High-level input
voltage
V_IH
3
V_DD V
Low-level input
voltage
V_IL
0
1.5 V
SCLK clock frequency f_SCLK
0
Rise times of SCLK, t_R
SDAT
400 kHz
0.3 µs
Fall times of SCLK, t_F
SDAT
0.3 µs
Set-up time DATA
Hold time DATA
Load capacitance
t_SU;DAT
t_HD;DAT
C_L
100
0
ns
ns
400 pF
Remark
Low FH-range
High FH-range
Fundamental
crystal type,
e.g. Saronix
9922 520 00282
See Application
information
f_SCLK = 400 kHz
Semiconductor Group
36
1998-02-01