SDA9361 Datasheet, PDF (6/47 Pages) Siemens Semiconductor Group – DDC-PLUS-Deflection Controller

SDA 9361
• Protection against missing V-deflection (CRT-protection)
• Selectable softstart of the H-output stage
• Clock generation on chip
• P-MQFP-44-2 package
• 5 V supply voltage
1.2 General Description
The SDA 9361 is a highly integrated deflection controller for CTV receivers with standard
or doubled line and field frequencies. It controls among others an horizontal driver circuit
for a flyback line output stage, a DC coupled vertical saw-tooth output stage and an east/
west raster correction circuit. All adjustable output parameters are Ι²C Bus controlled.
Inputs are HSYNC and VSYNC. The HSYNC signal is the reference for the internal clock
system which includes the Φ1 and Φ2 control loops.
1.3 Pin Configuration
V_DD(A3)
HSYNC
V_REFC
V_SS(A3)
V_DD(D)
V_SS(D)
SSD
V_SS(A4)
LF
V_DD(A4)
VOFFD
33 32 31 30 29 28 27 26 25 24 23
34
22
35
21
36
20
37
19
38
18
39
17
40
16
41
15
42
14
43
13
44
12
1 2 3 4 5 6 7 8 9 10 11
VD-
VD+
E/W
V_DD(A2)
V_REFP
V_REFN
V_SSA(1)
ABL
D/A
V_DDA(1)
HPROT
UEP10278
Figure 1
Semiconductor Group
6
1998-02-01