SDA9361 Datasheet, PDF (21/47 Pages) Siemens Semiconductor Group – DDC-PLUS-Deflection Controller

SDA 9361
NL2 ... NL0: Number of lines per field when NR = 1 and no vertical sync
at the input is detected
NL2
NL1
NL0
Number of Lines per Field
0
0
0
262.5
0
0
1
312.5
0
1
0
525
0
1
1
562.5
1
X
X
625
The Internal PLL Control Byte includes the following bits:
HSWID GENMOD VCR INCR4 INCR3 INCR2
INCR1
INCR0
HSWID:
Maximum width of HSYNC
0: 6.1 µs
for low FH-range
3.1 µs
for high FH-range
1: 8.8 µs
for low FH-range
4.0 µs
for high FH-range
GENMOD:
Clock generator mode
0: normal PLL mode
1: generator mode (fixed frequency output, controlled by INCR..)
VCR:
PLL filter optimized for
0: TV mode
1: VCR mode
INCR4 ... 0:
Nominal PLL output frequency
for low FH-range:
INCR = INT((FH _* 110592) / FQ - 64.625)
for high FH-range:
INCR = INT((FH _* 55296) / FQ - 64.625)
(for typical values see table below)
Semiconductor Group
21
1998-02-01