SDA9361 Datasheet, PDF (22/47 Pages) Siemens Semiconductor Group – DDC-PLUS-Deflection Controller

SDA 9361
specified range for:
GENMOD = 0: 6 ≤ INCR ≤ 14
GENMOD = 1: 3 ≤ INCR ≤ 18
(FQ = 24.576 MHz)
Application
PAL
NTSC
PAL (100 Hz)
NTSC (120 Hz)
ATV
MUSE
Macintosh
Default value: INCR = 6
FH[Hz]
15625
15750
31250
31500
32400
33750
35000
INCR
6
6
6
6
8
11
14
Warning:
1)A change of INCR or 2FH causes spontaneous changes of the generated clock
frequency greater than the specified 4.5 %.
Switching from PLL mode to Generator mode (GENMOD) with constant INCR
values does not result in exceeding the specified frequency deviation range.
2)If pin SSD has H-level the output signal HD starts immediately after power on. In
this case the starting horizontal frequency is either 15.75 kHz (if SELFH1_2 has
H-level or if SELFH1_2 and FH1_2 have L-level) or 31.5 kHz (if SELFH1_2 has
L-level and FH1_2 H-level). Starting with Muse or Macintosh standard requires
L-level at SSD so that INCR can be changed before enabling HD with HDE = 1.
3)Using external clock at pin 1, CLKI, (pin 32, CLEXT = 1): no internal protection
against missing clock pulses is provided.
4)In order to guarantee error free operation of the build in soft start circuit the input
frequency has to be inside the lock range of the PLL (+/-4.5 % of standard input
frequency)
Semiconductor Group
22
1998-02-01