SDA9361 Datasheet, PDF (5/47 Pages) Siemens Semiconductor Group – DDC-PLUS-Deflection Controller

DDC-PLUS-Deflection Controller
SDA 9361
MOS
1
Overview
1.1 Features
• Deflection - Protection - 16:9 / 4:3
• No external clock needed
• Φ1 PLL and Φ2 PLL on chip
• Ι²C-Bus alignment of all deflection parameters
• All EW-, V- and H- functions
P-MQFP-44-2
• PW EHT compensation
• PH EHT compensation
• Compensation of H-phase deviation (e.g. caused by white bar)
• Upper/lower EW-corner correction separately adjustable
• V-angle correction: Vertical frequent linear modulation of H-phase
• V-bow correction: Vertical frequent parabolic modulation of H-phase
• Three reduced V-scan modes (75 %, 66 %, 50 % V-size) adjustable by only 2 Bits
• H-frequent PWM output signal for general purpose
• H- and V-blanking time adjustable
• Partial overscan adjustable to hide the cut off control measuring lines in the
reducedscan modes
• Stop/start of vertical deflection adjustable to fill out the 16/9 screen with different
letterbox formats without annoying overscan
• Control signal SCAN as reference for vertical positioning of OSD, PIP etc.
• Vertical noise reduction with memory
• Standard and doubled line frequencies for NTSC and PAL, MUSE standard,
ATV standard, HDTV standard
• Self adaptation of V-frequency/number of lines per field between 192 and 680 for each
possible line frequency
• Protection against EHT run away (X-rays protection)
Type
SDA 9361
Semiconductor Group
Ordering Code
Q67107-H5167-A703
5
Package
P-MQFP-44-2
1998-02-01