SDA9361 Datasheet, PDF (14/47 Pages) Siemens Semiconductor Group – DDC-PLUS-Deflection Controller

SDA 9361
2.3 Reset Modes
The circuit is completely reset at power-on/off (timing diagram see figure 11) or if the
pin RESN has L-level (timing diagram see figure 12). During standby operation some
parts of the circuit are not affected (timing diagram see figure 12):
HD output
H-protection
V-protection
Ι²C interface (SDA,
SCL)
Ι²C register
01_H...1C_H, 1F_H
Ι²C register 00_H,
1D_H, 1E_H, 44_H...48_H
Status Bit PONRES
V_REFP, V_REFH. V_REFL
CPU
Power-On-Reset
Low
Inactive
Inactive
Tristate
External Reset
(pin RESN = Low)
Low
Inactive
Inactive
Tristate
Standby Mode
(I²C Bit STDBY = 1)
Active
Inactive
Inactive
Ready
Set to default values Set to default values Set to default values
Set to default values Set to default values Not affected
Set to 1¹⁾
Not affected
Inactive
Set to 1¹⁾
Not affected
Inactive
Not affected
Inactive
Inactive
1) _{Can only be read after Power-On-Reset is finished}
Note: Power-On-Reset and RESN = Low state are deactivated after ca. 32 cycles of the
X1/X2 oscillator clock and ca. 42 cycles of the CLL clock.
Standby state is deactivated after ca. 42 cycles of the CLL clock.
Semiconductor Group
14
1998-02-01