SDA9361 Datasheet, PDF (27/47 Pages) Siemens Semiconductor Group – DDC-PLUS-Deflection Controller

SDA 9361
Additional to the control items Vertical angle, Vertical bow and Horizontal shift, this
product influences the horizontal phase at the output HD according to the following
equation:
∆φ
=
∆V_ABL
*
A-----F---C------E----H-----T-----c---o---m-----p----e---n---s---a----t-i--o---n--
64
*
-⁵---²----¹---⁾
CLL
(if RABL = 0)
∆φ
=
∆V_ABL
*
A-----F---C------E----H-----T-----c---o---m-----p----e---n---s---a----t-i--o---n--
256
*
C^-5---2-L^---1-L^--)
(if RABL = 1)
∆φ
∆V_ABL
CLL
:variation of horizontal phase at the output HD
(positive values: shift left, negatives values: shift right)
:variation of ABL input voltage (units: Volt)
:864 _* F_H
1) _{The factor 52 depends on VREFP}
Vertical Blanking Time (VBT)
VBT defines the vertical blanking pulse VBL which is part of the output signal SCP. VBL
is synchronized with the leading edge of HSYNC. It always starts and stops at the
beginning of line and never in the center.
a) Case of STE = 0
In this case the control item Vertical blanking time defines the duration of the
V-blanking pulse (VBL) exactly in number of lines. Because of IC internal limitations
16 through 127 lines can be blanked. If BSE = 0 the control item Vertical blanking
time is disabled and always 21 lines (default value if disabled) are blanked.
After power on the control bit BSE is 0. Therefore 21 lines will be blanked before any
programming of the IC. If Vertical Blanking Time is less or equals 21 lines, VBL
starts (point A in fig. above) always 0 ... 0.5 line (new odd field) or 0.5 ... 1 line (new
even field) prior to the vertical flyback. Otherwise VBL is concentric to a fictitious
vertical flyback period of 21 lines, that means VBL starts (VBT - 21) / 2 lines at the
end of an odd field or (VBT - 20) / 2 at the end of an even field prior to point A.
Possible start points are only the beginning of line.
Semiconductor Group
27
1998-02-01