M30218 Datasheet, PDF (98/179 Pages) Mitsubishi Electric Semiconductor – M30218 Group

Clock asynchronous serial I/O (UART) mode
Mitsubishi microcomputers
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Clock asynchronous serial I/O (UART) mode
The UART allows transmitting and receiving data after setting the desired transfer rate and transfer data
format. Tables GA-3 lists the specifications of the UART mode. Figure GA-11 shows the UARTi transmit/
receive mode register.
Table GA-3. Specifications of clock synchronous serial I/O mode
Item
Transfer data format
Transfer clock
Transmission/reception control
Transmission start condition
Reception start condition
Interrupt request
generation timing
Error detection
Specification
•Character bit (transfer data): 7 bits, 8 bits or 9 bits as selected
•Start bit: 1 bit
•Parity bit: Odd, even or nothing as selected
•Stop bit: 1 bit or 2 bits as selected
•When internal clock is selected (bit 3 at addresses 03A016, 03A816 = “0”) :
fi/16(n+1) (Note 1) fi = f1, f8, f32
•When external clock is selected (bit 3 at addresses 03A016, 03A816 =“1”) :
fEXT/16(n+1) (Note 1) (Note 2)
_______
_______
_______ _______
•CTS function/RTS function/CTS, RTS function chosen to be invalid
•To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1”
- Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”
_______
_______
- When CTS function is selected, CTS input level = “L”
•To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 03A516, 03AD16) = “1”
- Start bit detection
•When transmitting
- Transmit interrupt cause select bits (bits 0,1 at address 03B016) = “0”:
Interrupts requested when data transfer from UARTi transfer buffer register to
UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 03B016) = “1”:
Interrupts requested when data transmission from UARTi transfer register is completed
•When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
•Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi receive
buffer register are read out
•Framing error
This error occurs when the number of stop bits set is not detected
•Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
•Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
select function
•Sleep mode selection
This mode is used to transfer data to and from one of multiple slave microcomputers
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also
that the UARTi receive interrupt request bit is not set to “1”.
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