M30218 Datasheet, PDF (34/179 Pages) Mitsubishi Electric Semiconductor – M30218 Group

Interrupt
Mitsubishi microcomputers
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt control register(Note2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DMiIC(i=0, 1)
ADIC
ASIOIC
FLDIC
SiTIC(i=0, 1)
SiRIC(i=0, 1)
TAiIC(i=0 to 4)
TBiIC(i=0 to 2)
Address
004B16 to 004C16
004E16
004F16
005016
005116, 005316
005216, 005416
005516 to 005916
005A16 to 005C16
When reset
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
Bit symbol
ILVL0
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
IR
Interrupt request bit
Function
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Interrupt not requested
1 : Interrupt requested
(Note1)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not
generate the interrupt request for that register. For details, see the
precautions for interrupts.
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
INTiIC(i=0 to 5)
Address
005D16 to 005F16
004716 to 004916
When reset
XX00X0002
Bit symbol
ILVL0
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
IR
POL
Interrupt request bit
Polarity select bit
Function
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
(Note1)
Reserved bit
Always set to “0”
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Note1 : This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not
generate the interrupt request for that register. For details, see the
precautions for interrupts.
Figure DD-3. Interrupt control registers
33