M30218 Datasheet, PDF (52/179 Pages) Mitsubishi Electric Semiconductor – M30218 Group

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Mitsubishi microcomputers
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses.
(a) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source
and destination both start at even addresses.
Figure EC-4 shows the example of the transfer cycles (a state of internal bus) for a source read. For
convenience, the destination write cycle is shown as one cycle and the source read cycles for the differ-
ent conditions are shown. In reality, the destination write cycle is subject to the same conditions as the
source read cycle, with the transfer cycle changing accordingly. When calculating the transfer cycle,
remember to apply the respective conditions to both the destination write cycle and the source read cycle.
(1) 8-bit transfers
16-bit transfers and the source address is even.
BCLK
Address
bus
RD signal
CPU use
Source Destination ^Dummy
cycle
WR signal
Data
bus
CPU use
Source Destination ^Dummy
cycle
CPU use
CPU use
(2) 16-bit transfers and the source address is odd
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use
Source Source + 1 Destination ^Dummy
cycle
Source Source + 1 Destination ^Dummy
cycle
CPU use
CPU use
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure EC-4. Example of transfer cycles for a source read (the state of internal bus)
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