M30218 Datasheet, PDF (40/179 Pages) Mitsubishi Electric Semiconductor – M30218 Group

Interrupt
Mitsubishi microcomputers
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer, at the time of acceptance of an interrupt request, is even or oDD- If the
content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at
a time. Figure DD-7 shows the operation of the saving registers.
Note: Stack pointer indicated by U flag.
(1) Stack pointer (SP) contains even number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Odd)
[SP] – 4 (Even)
Program counter (PCL)
[SP] – 3(Odd)
Program counter (PCM)
[SP] – 2 (Even)
Flag register (FLGL)
[SP] – 1(Odd)
[SP] (Even)
Flag register Program
(FLGH) counter (PCH)
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
Finished saving registers
in two operations.
(2) Stack pointer (SP) contains odd number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 4(Odd)
Program counter (PCL)
[SP] – 3 (Even)
Program counter (PCM)
[SP] – 2(Odd)
Flag register (FLGL)
[SP] – 1 (Even)
[SP] (Odd)
Flag register Program
(FLGH) counter (PCH)
(3)
(4) _{Saved simultaneously,}
all 8 bits
(1)
(2)
Finished saving registers
in four operations.
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure DD-7. Operation of saving registers
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