M30218 Datasheet, PDF (7/179 Pages) Mitsubishi Electric Semiconductor – M30218 Group

Pin Description
Mitsubishi microcomputers
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin name
VCC, VSS
CNVSS
Signal name
Power supply
input
CNVSS
I/O type
Input
RESET
Reset input
Input
Function
Supply 2.7V(Note1) to 5.5 V to the VCC pin. Supply 0 V to the VSS pin.
Connect a bypass capacitor across the VCC pin and VSS pin.
Connect it to the VSS pin.
A “L” on this input resets the microcomputer.
XIN
XOUT
AVCC
Clock input
Clock output
Input
Output
Analog power
supply input
These pins are provided for the main clock generating circuit.Connect
a ceramic resonator or crystal between the XIN and the XOUT pins. To
use an externally derived clock, input it to the XIN pin and leave the
XOUT pin open.
This pin is a power supply input for the A-D converter. Connect this
pin to VCC.
AVSS
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this
pin to VSS.
VREF
VEE
P00/FLD16 to
P07/FLD23
Reference
voltage input
pull-down
power source
Output port P0
Input
Output
P10/FLD24 to Output port P1 Output
P17/FLD31
This pin is a reference voltage input for the A-D converter.
Apply voltage supplied to pull-down resistors of ports P0 to P1,P5,P6.
This is an 8-bit CMOS output port and high-breakdown-voltage P-
channel open-drain output structure. A pull-down resistor is built in
between port P0 and VEE pin. At reset, this port is set to VEE level. P0
function as FLD controller output pins as selected by software.
This is an 8-bit output port equivalent to P0. Pins in this port also
function as FLD controller output pins as selected by software.
P20/FLD32 to Output port P2 Output
P27/FLD39
This is an 8-bit output port equivalent to P0. A pull-down resistor is not
built in between P2 and VEE pin. Pins in this port also function as FLD
controller output pins as selected by software.
P30/FLD40 to I/O port P3
P37/FLD47
P40/FLD48 to I/O port P4
P47/FLD56
Input/output
Input/output
This is an 8-bit I/O port. A pull-down resistor is not built in between P3
and VEE pin. It has an input/output port direction register that allows the
user to set each pin for input or output. This is low-voltage input level,
and high-breakdown-voltage P-channel open-drain output structure.
Pins in this port also function as FLD controller output pins as selected
by software.
This is an 8-bit I/O port equivalent to P3. This is low-voltage input level.
P40 to P43 is high-breakdown-voltage P-channel open-drain output
structure, P44 to P47 is CMOS output. A pull-down resistor is not built
in between P4(P40 to P43) and VEE pin. Pins in this port also function
as FLD controller output pins as selected by software. P44 to P47 also
function as UART0 I/O pins as selected by software. When set for
input, the user can specify in units of four bits by software whether or
not they are tied to a pull-up resistor.
P50/FLD8 to
P57/FLD15
P60/FLD0 to
P67/FLD7
Output port P5 Output
Output port P6 Output
This is an 8-bit output port equivalent to P0. Pins in this port also
function as FLD controller output pins as selected by software.
This is an 8-bit output port equivalent to P0. Pins in this port also
function as FLD controller output pins as selected by software.
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