M30218 Datasheet, PDF (113/179 Pages) Mitsubishi Electric Semiconductor – M30218 Group

Serial I/O2
Mitsubishi microcomputers
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) SRDY2 output signal
The SRDY2 output is a transmit/receive enable signal which informs the serial transfer destination that
transmit/receive is ready. In the initial status[serial I/O initialization bit (bit 4 of address 034216) = “0” ],
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the SRDY2 output goes to “L” (or the SRDY2 output goes to “H”). When the transmitted data is written to
__________
the serial I/O2 register (address 034616), the SRDY2 output goes to “H” (or the SRDY2 output goes to
“L”). When a transmit/receive operation is started and the transfer clock goes to “L”, the SRDY2 output
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goes to “L” (or the SRDY2 output goes to “H”).
•Serial operation used SRDY2 output
Operation mode
Transfer clock
: 8-bit serial I/O mode
: Internal synchronous clock
Tc
Internal clock
"H"
SRDY2
(output) "L"
SCLK2i
(i = 1, 2) (output)
SOUT2
D0 D1 D2 D3 D4 D5 D6 D7
Serial transfer status flag "1"
(bit 5 at address 034416) _"0"
Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816
Figure GA-12. SRDY2 Output Operation
(5) SRDY2 input signal
The SRDY2 input is a signal for receiving a transmit/receive ready completion signal from the serial
transfer destination. The SRDY2 input signal becomes valid only when the SRDY2 input and the SBUSY2
output are used.
When the internal synchronous clock is selected, input a “L” level signal into the SRDY2 input (or a “H”
__________
level signal into the SRDY2 input) in the initial status[serial I/O initialization bit (bit 4 of address 034216)
__________
= “0” ]. When a “H” level signal is input into the SRDY2 input (or a “L” level signal is input into the SRDY2
input) for a period of 1.5 cycles or more of transfer clock, transfer clocks are output from the SCLK2i (i =
__________
1, 2) output and a transmit/receive operation is started. When SRDY2 input is driven “L” (or SRDY2 input
is driven “H”) during transmit/receive operation, the transfer clock being output from SCLK2i (i = 1, 2)
remains active until after the system finishes sending or receiving the designated number of bits,
without stopping the transmit/receive operation immediately.
The handshake unit of the 8-bit serial I/O is 8 bits, and that of the automatic transfer serial I/O is 8 bits.
When the external synchronous clock is selected, the SRDY2 input becomes one of the triggers to
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output the SBUSY2 signal. To start a transmit/receive operation (SBUSY2 output: “L”, (or SBUSY2 output:
__________
“H”)), input a “H” level signal into the SRDY2 input (or a “L” level signal into the SRDY2 input,) and also
write transmit data into the serial I/O2 register (address 034616).
•Serial operation used SRDY2 input
Operation mode
Transfer clock
: 8-bit serial I/O mode
: Internal synchronous clock
Tc
Internal clock
Serial transfer status flag ^"1"
(bit 5 at address 034416) _"0"
"H"
SRDY2
(input) "L"
SCLK2i
(i = 1, 2) (output)
SOUT2
1.5 cycle or more
D0 D1 D2 D3 D4 D5 D6 D7
Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816
Figure GA-13. SRDY2 Input Operation
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