M30218 Datasheet, PDF (95/179 Pages) Mitsubishi Electric Semiconductor – M30218 Group

Clock synchronous serial I/O mode
Mitsubishi microcomputers
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Example of transmit timing (when internal clock is selected)
Transfer clock
“1”
Transmit enable
bit (TE)
“0”
Transmit buffer ^{“1”}
empty flag (Tl) _{“0”}
“H”
CTSi
“L”
CLKi
Tc
Data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register
TCLK
Stopped pulsing because CTS = “H”
Stopped pulsing because transfer enable bit = “0”
TxDi
Transmit
“1”
register empty
flag (TXEPT)
“0”
Transmit interrupt ^{“1”}
request bit (IR) _{“0”}
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Cleared to “0” by software, or when an interrupt request is accepted.
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi's count source (f1, f8, f32)
n: value set to BRGi
• Example of receive timing (when external clock is selected)
Receive enable ^{“1”}
bit (RE)
“0”
Transmit enable ^{“1”}
bit (TE)
“0”
Dummy data is set in UARTi transmit buffer register
Transmit buffer ^{“1”}
empty flag (Tl) _{“0”}
“H”
RTSi
“L”
Transferred from UARTi transmit buffer register to UARTi transmit register
1 / fEXT
CLKi
Receive data is taken in
RxDi
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5
Receive complete ^{“1”}
flag (Rl)
“0”
Transferred from UARTi receive register
to UARTi receive buffer register
Read out from UARTi receive buffer register
Receive interrupt “1”
request bit (IR) _{“0”}
Cleared to “0” by software, or when an interrupt request is accepted.
fEXT: frequency of external clock
Shown in ( ) are bit symbols.
The above timing applies to the following settings.
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”.
Meet the following conditions when the CLK input before
data reception = “H”
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UARTi transmit buffer register
Figure GA-7. Typical transmit/receive timings in clock synchronous serial I/O mode
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