M16C62N Datasheet, PDF (97/213 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clock synchronous serial I/O mode
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.14.2
and 1.14.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.14.10 shows the
UARTi transmit/receive mode register. Clock synchronous serial I/O mode cannot be used in UART2.
Table 1.14.2. Specifications of clock synchronous serial I/O mode (1)
Item
Specification
Transfer data format
• Transfer data length: 8 bits
Transfer clock
• When internal clock is selected (bit 3 at addresses 03A016, 03A816 = “0”)
: fi/ 2(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 03A016, 03A816 = “1”)
: Input from CLKi pin
_______
_______
_______
_______
Transmission/reception control • CTS function, RTS function, CTS and RTS function invalid: selectable
Transmission start condition
• To start transmission, the following requirements must be met:
_ _{Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1”}
_ _{Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”}
_______
_______
_ _{When CTS function selected, CTS input level = “L”}
• Furthermore, if external clock is selected, the following requirements must also be met:
_ _{CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = “0”}
: CLKi input level = “H”
_ _{CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = “1”}
: CLKi input level = “L”
Reception start condition
• To start reception, the following requirements must be met:
_ _{Receive enable bit (bit 2 at addresses 03A516, 03AD16) = “1”}
_ _{Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1”}
_ _{Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”}
• Furthermore, if external clock is selected, the following requirements must
also be met:
_ _{CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = “0”}
: CLKi input level = “H”
_ _{CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = “1”}
: CLKi input level = “L”
Interrupt request
generation timing
• When transmitting
_ _{Transmit interrupt cause select bit (bits 0, 1 at address 03B016) = “0”}
: Interrupts requested when data transfer from UARTi transfer buffer register
to UARTi transmit register is completed
_ _{Transmit interrupt cause select bit (bits 0, 1 at address 03B016) = “1”}
: Interrupts requested when data transmission from UARTi transfer register
is completed
• When receiving
_ _{Interrupts requested when data transfer from UARTi receive register to}
UARTi receive buffer register is completed
Error detection
• Overrun error (Note 2)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit does not change.
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