M16C62N Datasheet, PDF (54/213 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Address Match Interrupt
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-
rupt enable flag (I flag) and processor interrupt priority level (IPL). For an address match interrupt, the value
of the program counter (PC) that is saved to the stack area varies depending on the instruction being
executed.
Figure 1.10.12 shows the address match interrupt-related registers.
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Address
000916
When reset
XXXXXX002
Bit symbol
Bit name
AIER0
Address match interrupt 0
enable bit
Function
0 : Interrupt disabled
1 : Interrupt enabled
AIER1 ^{Address match interrupt 1} 0 : Interrupt disabled
enable bit _{1 : Interrupt enabled}
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
RW
Address match interrupt register i (i = 0, 1)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
Symbol
b0 _RMAD0
RMAD1
Address
001216 to 001016
001616 to 001416
When reset
X0000016
X0000016
Function
Values that can be set R W
Address setting register for address match interrupt 0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Figure 1.10.12. Address match interrupt-related registers
53