M16C62N Datasheet, PDF (95/213 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Serial I/O
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
UCON
Address
03B016
When reset
X00000002
Bit
symbol
Bit name
U0IRS UART0 transmit
interrupt cause select bit
Function
(During clock synchronous
serial I/O mode)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
Function
(During UART mode)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
RW
U1IRS UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U0RRM UART0 continuous
receive mode enable bit
U1RRM UART1 continuous
receive mode enable bit
CLKMD0 CLK/CLKS select bit 0
CLKMD1 CLK/CLKS select
bit 1 (Note)
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
0 : Normal mode
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
Must always be “0”
Must always be “0”
Invalid
Must always be “0”
Reserved bit
Must always be set to “0”
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”.
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR
Address
037716
When reset
8016
Bit
symbol
Bit name
Function
(During clock synchronous
serial I/O mode)
Function
(During UART mode)
IICM IIC mode select bit
0 : Normal mode
1 : I²C mode
Must always be “0”
ABC Arbitration lost detecting 0 : Update per bit
flag control bit
1 : Update per byte
Must always be “0”
RW
BBS Bus busy flag
0 : STOP condition detected Must always be “0”
1 : START condition detected
(Note 1)
LSYN SCLL sync output
enable bit
0 : Disabled
1 : Enabled
Must always be “0”
ABSCS ^{Bus collision detect}
sampling
clock select bit
Must always be “0”
0 : Rising edge of transfer
clock
1 : Underflow signal of timer A0
ACSE
Auto clear function
select bit of transmit
enable bit
SSS ^{Transmit start condition}
select bit
Must always be “0”
Must always be “0”
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
0 : Ordinary
1 : Falling edge of RxD2
SDDS
SDA digital delay select
bit (Note 2)
0 : Must always be “0”
Must always be “0”
when not using I²C mode
1 : Digital delay output
is selected
Note 1: Nothing but "0" may be written.
Note 2: When not in I²C mode, do not set this bit by writing a “1”. During normal mode, fix it to “0”. When this
bit = “0”, UART2 special mode register 3 (U2SMR3 at address 037516) bits 7 to 5 (DL2 to DL0 = SDA
digital delay setup bits) are initialized to “000”. Also, when SDDS = “0”, the U2SMR3 register cannot be
read or written to.
Note 3: UART2 clock synchronous serial I/O mode cannot be used in M16C/62N (80-pin version) group.
Figure 1.14.8. Serial I/O-related registers (5)
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