M16C62N Datasheet, PDF (114/213 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clock asynchronous serial I/O (UART) mode
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(a) Function for outputting a parity error signal
During reception, with the error signal output enable bit (bit 7 of address 037D16) assigned “1”, you
can output an “L” level from the TXD2 pin when a parity error is detected. And during transmission,
comparing with the case in which the error signal output enable bit (bit 7 of address 037D16) is as-
signed “0”, the transmission completion interrupt occurs in the half cycle later of the transfer clock.
Therefore parity error signals can be detected by a transmission completion interrupt program. Figure
1.14.22 shows the output timing of the parity error signal.
• LSB first
Transfer ^{“H”}
clock “L”
RxD2
“H”
“L”
TxD2
“H”
“L”
Receive ^{“1”}
complete flag “0”
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Hi-Z
ST : Start bit
P : Even Parity
SP : Stop bit
Figure 1.14.22. Output timing of the parity error signal
(b) Direct format/inverse format
Connecting the SIM card allows you to switch between direct format and inverse format. If you choose
the direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted
and output from TxD2.
Figure 1.14.23 shows the SIM interface format.
Transfer
clcck
TxD2
(direct)
TxD2
(inverse)
D0 D1 D2 D3 D4 D5 D6 D7 P
D7 D6 D5 D4 D3 D2 D1 D0 P
P : Even parity
Figure 1.14.23. SIM interface format
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