M16C62N Datasheet, PDF (165/213 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

CPU Rewrite Mode (Flash Memory Version)
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode.
(1) Operation speed
During CPU rewrite mode, set the BCLK as shown below using the main clock divide ratio select bit
(bit 6 at address 000616 and bits 6 and 7 at address 000716):
6.25 MHz or less when wait bit (bit 7 at address 000516) = 0 (without internal access wait state)
10.0 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state)
(2) Instructions inhibited against use
The instructions listed below cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
(3) Interrupts inhibited against use
The address match interrupt cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory. If interrupts have their vector in the variable vector table, they can be
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used by transferring the vector into the RAM area. The NMI and watchdog timer interrupts can be
used to automatically initialize the flash identification register and flash memory control register 0 to
“0”, then return to normal operation. However, these two interrupts' jump addresses are located in the
fixed vector table and there must exsist a routine to be executed. Since the rewrite operation is halted
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when an NMI or watchdog timer interrupts occurs, you must reset the CPU rewite mode select bit to
“1” and the perform the erase/program operation again.
(4) Access disable
Write to CPU rewrite mode select bit and user ROM area select bit only when executing out of an area
other than the internal flash memory.
(5) How to access
For CPU rewrite mode select bit and lock bit disable select bit to be set to “1”, the user needs to write
a “0” and then a “1” to it in succession. When it is not this procedure, it is not enacted in “1”. This is
necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Write to
CPU rewrite mode select bit and user ROM area select bit only when executing out of an area other
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than the internal flash memory.Also only when NMI pin is “H” level.
(6)Writing in the user ROM area
If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite mode,
those blocks may not be correctly rewritten and it is possible that the flash memory can no longer be
rewritten after that. Therefore, it is recommended to use the standard serial I/O mode or parallel I/O
mode to rewrite these blocks.
(7)Using the lock bit
To use the CPU rewrite mode, use a boot program that can set and cancel the lock command.
(8) Internal reserved area expansion bit (Bit 3 at address 000516)
To use the products which RAM size is over 15 Kbytes or flash memory size is over 192 Kbytes,
change into the CPU rewrite mode after setting the internal reserved area expansion bit (bit 3 at
address 000516) to “1”. Even if the CPU rewrite mode select bit (bit 1 at address 03B716) is set to “1”,
the internal reserved area expansion bit (bit 3 at address 000516) is not set to “1” automatically.
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