M16C62N Datasheet, PDF (171/213 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

CPU Rewrite Mode (Flash Memory Version)
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Data Protect Function (Block Lock)
Each block in Figure 1.28.1 has a nonvolatile lock bit to specify that the block be protected (locked)
against erase/write. The lock bit program command is used to set the lock bit to 0 (locked). The lock bit of
each block can be read out using the read lock bit status command.
Whether block lock is enabled or disabled is determined by the status of the lock bit and how the flash
memory control register 0’s lock bit disable select bit is set.
(1) When the lock bit disable select bit = “0”, a specified block can be locked or unlocked by the lock bit
status (lock bit data). Blocks whose lock bit data = 0 are locked, so they are disabled against erase/
write. On the other hand, the blocks whose lock bit data = “1” are not locked, so they are enabled for
erase/write.
(2) When the lock bit disable select bit = 1, all blocks are nonlocked regardless of the lock bit data, so
they are enabled for erase/write. In this case, the lock bit data that is “0” (locked) is set to “1”
(nonlocked) after erasure, so that the lock bit-actuated lock is removed.
Status Register
The status register shows the operating state of the flash memory and whether erase operations and
programs ended successfully or in error. It can be read in the following ways.
(1) By reading an arbitrary even address from the user ROM area after writing the read status register
command (7016)
(2) By reading an arbitrary even address from the user ROM area in the period from when the program
starts or erase operation starts to when the read array command (FF16) is input
Table 1.29.2 shows the status register.
Also, the status register can be cleared in the following way.
(1) By writing the clear status register command (5016)
After a reset, the status register is set to “8016”.
Each bit in this register is explained below.
Sequencer status (SR7)
After power-on, the sequencer status is set to 1(ready).
The sequencer status indicates the operating status of the device. This status bit is set to “0” (busy)
during write or erase operation and is set to “1” upon completion of these operations.
Erase status (SR5)
The erase status informs the operating status of erase operation to the CPU. When an erase error
occurs, it is set to “1”.
The erase status is reset to “0” when cleared.
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