M16C62N Datasheet, PDF (42/213 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Interrupt
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level select
bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated
by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located
in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are
located in the flag register (FLG).
Figure 1.10.3 shows the interrupt control registers.
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