M16C62N Datasheet, PDF (163/213 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

CPU Rewrite Mode (Flash Memory Version)
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bit 5 of the flash memory control register 0 is a user ROM area select bit which is effective in only boot
mode. If this bit is set to “1” in boot mode, the area to be accessed is switched from the boot ROM area to
the user ROM area. When the CPU rewrite mode needs to be used in boot mode, set this bit to “1”. Note
that if the microcomputer is booted from the user ROM area, it is always the user ROM area that can be
accessed and this bit has no effect. When in boot mode, the function of this bit is effective regardless of
whether the CPU rewrite mode is on or off. Write to this bit only when executing out of an area other than
the internal flash memory.
Bit 6 of the flash memory control register 0 is the program status flag used exclusively to read the operating
status of the auto program operation. If a program error occurs, it is set to “1”. Otherwise, it is “0”.
Bit 7 of the flash memory control register 0 is the erase status flag used exclusively to read the operating
status of the auto erase operation. If an erase error occurs, it is set to “1”. Otherwise, it is “0”.
Flash identification register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FIDR
Address
03B416
When reset
0016
Bit symbol
Bit name
Function
FIDR0 Flash identification value Flash value output
HND: 0016
Procedure
(1) Write FF16 to the address 03B416
(2) Read address 03B416
Read value = FF16 ••• DINOR flash memory
Read value = 0016 ••• HND flash memory
RR WW
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
FMR0
Address
03B716
When reset
XX0000012
Bit symbol
Bit name
FMR00 RY/BY status flag
Function
0: Busy (being written or erased)
1: Ready
RR WW
FMR01
FMR02
FMR03
CPU rewrite mode
select bit (Note 1)
0: Normal mode
(Software commands invalid)
1: CPU rewrite mode
(Software commands acceptable)
Lock bit disable
select bit (Note 2)
0: Block lock by lock bit data is
enabled
1: Block lock by lock bit data is
disabled
Flash memory reset bit 0: Normal operation
(Note 3)
1: Reset
Reserved bit
Must always be set to “0”
FMR05
FMR06
FMR07
User ROM area select bit _{0: Boot ROM area is accessed}
(Note 4) (Effective in only _{1: User ROM area is accessed}
boot mode)
Program status flag
0: Pass
1: Error
Erase status flag
0: Pass
1: Error
Note 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession.
When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no
interrupt or DMA transfer will be executed during the interval. Write to this bit only when
executing out of an area other than the internal flash memory. Also only when NMI pin is
“H” level. Clear this bit to “0” after read array command.
Note 2: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession
when the CPU rewrite mode select bit = “1”. When it is not this procedure, it is not
enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be
executed during the interval.
Note 3: Effective only when the CPU rewrite mode select bit = 1. After write “1”, write “0” when
RY/BY status flag is “1”.
Note 4: Write to this bit only when executing out of an area other than the internal flash memory.
Figure 1.29.1. Flash identification register and flash memory control register 0
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