M16C62N Datasheet, PDF(127/213 Page) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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M16C62N Datasheet, PDF (127/213 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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S I/O3, 4

Mitsubishi microcomputers

M16C / 62N Group (80-pin)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Functions for setting an SOUTi initial value

When using an external clock for the transfer clock, the SOUTi pin output level during a non-transfer

time can be set to the high or the low state. Figure 1.14.32 shows the timing chart for setting an SOUTi

initial value and how to set it.

(Example) With âHâ selected for SOUTi:

Signal written to the S I/Oi

transmit/receive register

SOUTi's initial value

set bit (SMi7)

S I/Oi port select bit

(SMi3)

S I/Oi port select bit SMi3 = 0

SOUTi initial value select bit

SMi7 = 1

(SOUTi: Internal âHâ level)

S I/Oi port select bit

SMi3 = 0 1

(Port select: Normal port SOUTi)

SOUTi (internal)

Port output

SOUTi terminal output

Initial value = âHâ (Note)

(i = 3, 4)

Setting the SOUTi Port selection

initial value to H (normal port SOUTi)

Note: The set value is output only when the external clock has been selected. When

initializing SOUTi, make sure the CLKi pin input is held âHâ level.

If the internal clock has been selected or if SOUT output disable has been set,

this output goes to the high-impedance state.

SOUTi terminal = âHâ output

Signal written to the S I/Oi register

=âLâ âHâ âLâ

(Falling edge)

SOUTi terminal = Outputting

stored data in the S I/Oi transmission/

reception register

Figure 1.14.32. Timing chart for setting SOUTiâs initial value and how to set it

S I/Oi operation timing

Figure 1.14.33 shows the S I/Oi operation timing

"H"

SI/Oi internal clock "L"

Transfer clock "H"

(Note 1) "L"

Signal written to the "H"

S I/Oi transmit/receive "L"

S I/Oi output SOUTi "H"

(i= 3, 4)

"L"

S I/Oi input SINi "H"

(i= 3, 4)

"L"

SI/Oi interrupt request "1"

bit

(i= 3, 4)

"0"

1.5 cycle (max)

Hiz

Note2

Hiz

Note 1: With the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the S I/Oi control register.

(i=3,4) (No frequency division, 8-division frequency, 32-division frequency.)

Note 2: With the internal clock selected for the transfer clock, the SOUTi pin becomes to the high-impedance state after the transfer finishes.

Note 3: Shown above is the case where the SOUTi (i = 3, 4) port select bit ="1".

Figure 1.14.33. S I/Oi operation timing chart

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