M16C62N Datasheet, PDF(13/213 Page) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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M16C62N Datasheet, PDF (13/213 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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CPU

Mitsubishi microcomputers

M16C / 62N Group (80-pin)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(3) Frame base register (FB)

Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.

(4) Program counter (PC)

Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.

(5) Interrupt table register (INTB)

Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector

table.

(6) Stack pointer (USP/ISP)

Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-

ured with 16 bits.

Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).

This flag is located at the position of bit 7 in the flag register (FLG).

(7) Static base register (SB)

Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.

(8) Flag register (FLG)

Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.5.2 shows the flag

â¢ Bit 0: Carry flag (C flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

â¢ Bit 1: Debug flag (D flag)

This flag enables a single-step interrupt.

When this flag is â1â, a single-step interrupt is generated after instruction execution. This flag is

cleared to â0â when the interrupt is acknowledged.

â¢ Bit 2: Zero flag (Z flag)

This flag is set to â1â when an arithmetic operation resulted in 0; otherwise, cleared to â0â.

â¢ Bit 3: Sign flag (S flag)

This flag is set to â1â when an arithmetic operation resulted in a negative value; otherwise, cleared to â0â.

â¢ Bit 4: Register bank select flag (B flag)

This flag chooses a register bank. Register bank 0 is selected when this flag is â0â ; register bank 1 is

selected when this flag is â1â.

â¢ Bit 5: Overflow flag (O flag)

This flag is set to â1â when an arithmetic operation resulted in overflow; otherwise, cleared to â0â.

â¢ Bit 6: Interrupt enable flag (I flag)

This flag enables a maskable interrupt.

An interrupt is disabled when this flag is â0â, and is enabled when this flag is â1â. This flag is cleared to

â0â when the interrupt is acknowledged.

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