M16C62N Datasheet, PDF (162/213 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

CPU Rewrite Mode (Flash Memory Version)
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Outline Performance (CPU Rewrite Mode)
In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by
software commands. Operations must be executed from a memory other than the internal flash memory,
such as the internal RAM.
When the CPU rewrite mode select bit (bit 1 at address 03B716) is set to “1”, transition to CPU rewrite mode
occurs and software commands can be accepted.
In the CPU rewrite mode, write to and read from software commands and data into even-numbered ad-
dress (“0” for byte address A0) in 16-bit units. Write data into even address in 16-bit units. Do not write 16-
bit data into odd address or data in 8-bit units. Always write 8-bit software commands into even-numbered
address. Commands are ignored with odd-numbered addresses.
Use software commands to control program and erase operations. Whether a program or erase operation
has terminated normally or in error can be verified by reading the status register. Read data from an even
address in the user ROM area when reading the status register.
Figure 1.29.1 shows the flash identification register and flash memory control register 0.
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Bit 0 of the flash memory control register 0 is the RY/BY status flag used exclusively to read the operating
status of the flash memory. During programming, erase and lock-bit programming operations, it is “0”.
Otherwise, it is “1”.
Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit. The CPU rewrite mode is
entered by setting this bit to “1”, so that software commands become acceptable. In CPU rewrite mode, the
CPU becomes unable to access the internal flash memory directly. Therefore, Write to this bit only when
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executing out of an area other than the internal flash memory. Also only when NMI pin is "H" level. To set
this bit to “1”, it is necessary to write “0” and then write “1” in succession. To set this bit to “0” by only writing
a “0” .
Bit 2 of the flash memory control register 0 is a lock bit disable select bit. By setting this bit to “1”, it is
possible to disable erase and write protect (block lock) effectuated by the lock bit data. The lock bit disable
select bit only disables the lock bit function; it does not change the lock data bit value. However, if an erase
operation is performed when this bit =“1”, the lock bit data that is “0” (locked) is set to “1” (unlocked) after
erasure. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession. This bit can be
manipulated only when the CPU rewrite mode select bit = “1”.
Bit 3 of the flash memory control register is the flash memory reset bit used to reset the control circuit of the
internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has
failed. When the CPU rewrite mode select bit is “1”, writing “1” for this bit resets the control circuit. To
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release the reset, it is necessary to set this bit to “0” when RY/BY status flag is “1”. Also when this bit is set
to “1”, power is not supplied to the internal flash memory, thus power consumption can be reduced. How-
ever, in this state, the internal flash memory cannot be accessed. To set this bit to “1”, it is necessary to
write “0” and then write “1” in succession when the CPU rewrite mode select bit is “1”. Use this bit mainly in
the low speed mode (when XCIN is the count source of BCLK).
When the CPU is shifted to the stop or wait modes, power to the internal flash memory is automatically shut
off. It is reconnected automatically when CPU operation is restored. Therefore, it is not particularly neces-
sary to set flash memory control register 0.
Figure 1.29.2b shows a flowchart for shifting to the low power dissipation mode. Always perform operation
as indicated in these flowcharts.
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