38K2 Datasheet, PDF (95/151 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K2 Group
b7
Fig. 140 Structure of PLL control register
b0
PLL control register
(PLLCON: address 0FF816)
Not used (return “0” when read)
USB clock division ratio selection bits
b4b3
0 0: Divided by 8 (fSYN = fUSB/8)
0 1: Divided by 6 (fSYN = fUSB/6)
1 0: Divided by 4 (fSYN = fUSB/4)
1 1: Not selected
PLL operation mode selection bits
b6b5
0 0: Not multiplied (fVCO = fXIN)
0 1: Double (fVCO = fXIN ✕ 2)
1 0: Quadruple (fVCO = fXIN ✕ 4)
1 1: Multiplied by 8 (fVCO = fXIN ✕ 8)
PLL Enable Bit
0: Disabled
1: Enabled
Rev.3.00 Oct 15, 2006 page 95 of 147
REJ03B0193-0300