38K2 Datasheet, PDF (37/151 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K2 Group
(1) Endpoint 00
b7
b0
000 00 00
EP00 stage register (EP00STG) [address 001916]
Bit symbol
Bit name
SETUP00 SETUP packet detection bit
b7:b1
Not used
Function
At reset _{R W}
H/W S/W
This bit is set to “1” at reception of SETUP packet.
1 1 OO
Writing “0” to this bit clears this bit if the next SETUP
token does not occur.
Writing “1” to this bit causes no state change of the
status flags.
Write “0” when writing.
– – OO
“0” is read when reading.
–: State remaining
Fig. 40 Structure of EP00 stage register
b7
000000
b0
EP00 control register 1 (EP00CON1) [address 001A16]
Bit symbol
Bit name
PID00 [1:0] Response PID bit
b7:b2
Not used
Fig. 41 Structure of EP00 control register 1
Function
b1 b0
0 0 : NAK
0 1 : Automatic response (ACK, NAK, DATA0, DATA1)
1 X : STALL
At occurrence of control transfer error:
B1 is set to “1” by the hardware.
At reception of SETUP token:
B1 and b0 are cleared to “0” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
H/W S/W
0–
––
RW
OO
OO
–: State remaining
b7
b0
0 0 0 0 0 0 0 EP00 control register 2 (EP00CON2) [address 001B16]
Bit symbol
Bit name
BVAL00
Buffer enable bit
b7:b1
Not used
Fig. 42 Structure of EP00 control register 2
Function
At reset _{R W}
H/W S/W
0 : NAK transmission (SIE is disabled to read a buffer.) 0 – O O
1 : Transmitting/receiving data set state (SIE is possible
to read from/write to a buffer.)
At reception of SETUP token:
This bit is cleared to “0” by the hardware.
Write “0” when writing.
– – OO
“0” is read when reading.
–: State remaining
Rev.3.00 Oct 15, 2006 page 37 of 147
REJ03B0193-0300