38K2 Datasheet, PDF (122/151 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K2 Group
qStatus Register 1 (SRD1)
The status register 1 indicates the status of serial communica-
tions, results from ID checks and results from check sum
comparisons. It can be read after the SRD by writing the read sta-
tus register command (7016). Also, status register 1 is cleared by
writing the clear status register command (5016).
Table 15 lists the definition of each status register 1 bit. This regis-
ter becomes “0016” when power is turned on and the flag status is
maintained even after the reset.
•Boot update completed bit (SR15)
This flag indicates whether the control program was downloaded
to the RAM or not, using the download function.
•Check sum consistency bit (SR12)
This flag indicates whether the check sum matches or not when a
program, is downloaded for execution using the download func-
tion.
•ID check completed bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands
cannot be accepted without an ID check.
•Data reception time out (SR9)
This flag indicates when a time out error is generated during data
reception. If this flag is attached during data reception, the re-
ceived data is discarded and the MCU returns to the command
wait state.
Table 15 Status register 1 (SRD1)
SRD1 bits
Status name
SR15 (bit7)
SR14 (bit6)
SR13 (bit5)
SR12 (bit4)
SR11 (bit3)
SR10 (bit2)
Boot update completed bit
Reserved
Reserved
Checksum match bit
ID check completed bits
SR9 (bit1)
SR8 (bit0)
Data reception time out
Reserved
Definition
“1”
“0”
Update completed
Not Update
-
-
-
-
Match
00
01
Mismatch
Not verified
Verification mismatch
10
Reserved
11
Verified
Time out
Normal operation
-
-
Rev.3.00 Oct 15, 2006 page 122 of 147
REJ03B0193-0300