38K2 Datasheet, PDF (86/151 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K2 Group
(6) Memory Channel Transmitting Operation
(1)-Cycle Mode
Memory channel transmitting operation (1) is shown bellow.
➀
➁
➂
➃
➄
➂’
➅
Address ExA0
A0 = “x”
A0 = “x”
Chip select ExCS
DMA acknowledge
ExDACK
Read ExRD
CS = “1”
Dack = “0”
➂
➃
CS = “1”
Dack = “0”
➂’
➅
Write ExWR
Data DQ0 to DQ7
#0
#1
Internal clock φ
DMA request
ExDREQ
mRD detection
mRD detection
Transmission completed
Mch_req
Mch_req
Transmit buffer TXBUF
#0
#1
➀
Operation enabled
Main sequencer
0
1
2
Memory channel operation
end interrupt
Internal memory access
req
3
4
5
req
Memory address
010016
Counter end
010116
010216
Acknowledgment of
internal memory access
ack
➁
ack
➄
<Initial setting>
External I/O configuration register
Memory channel operation mode register
Memory address counter
End address register
Set as necessary.
MC_DIR[1:0] (Memory channel direction control) = 102 (Transmit mode)
Burst (burst) = “0” (Cycle mode)
(Example) 010016
(Example) 010116
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
➀ In the memory channel transmit mode when the command for enabling operation is written, operation starts (main sequencer starts) and an internal
memory access sequence which synchronized with a rise of φ is activated.
➁ A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased and assertion of the memory channel request is made.
➂ When the external MCU bus is in the condition of ExCS = “L” and ExA0 = “L” or a fall of ExRD is detected in the condition of ExDACK = “L”, negation of the
memory channel request which synchronized with a rise of φ is made.
➃ When a rise of ExRD is detected, an internal memory access sequence which synchronized with a rise of φ is activated.
➄ A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased and assertion of the memory channel request is made.
When the read operation from the end address has been completed, the transition to the status to wait the memory channel operation end occurs.
➅ When a rise of ExRD is detected, the memory channel operation sequence ends and the memory channel operation end interrupt is generated.
Fig. 127 Memory channel tranmitting operation (1)
Rev.3.00 Oct 15, 2006 page 86 of 147
REJ03B0193-0300