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38K2 Datasheet, PDF (101/151 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER | |||
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38K2 Group
Outline Performance (CPU Rewrite Mode)
CPU rewrite mode is usable in the single-chip or Boot mode. The
only User ROM area can be rewritten in CPU rewrite mode.
In CPU rewrite mode, the CPU erases, programs and reads the in-
ternal flash memory as instructed by software commands. This
rewrite control program must be transferred to a memory such as
the internal RAM before it can be executed.
The MCU enters CPU rewrite mode by applying 4.50 V to 5.25 V
to the CNVSS pin and setting â1â to the CPU Rewrite Mode Select
Bit (bit 1 of address 0FFE16). Software commands are accepted
once the mode is entered.
Use software commands to control program and erase operations.
Whether a program or erase operation has terminated normally or
in error can be verified by reading the status register.
Figure 147 shows the flash memory control register.
Bit 0 is the RY/BY status flag used exclusively to read the operat-
ing status of the flash memory. During programming and erase
operations, it is â0â (busy). Otherwise, it is â1â (ready). This is
equivalent to the RY/BY pin function in parallel I/O mode.
Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to
â1â, the MCU enters CPU rewrite mode. Software commands are
accepted once the mode is entered. In CPU rewrite mode, the
CPU becomes unable to access the internal flash memory directly.
Therefore, use the control program in a memory other than inter-
nal flash memory for write to bit 1. To set this bit to â1â, it is
necessary to write â0â and then write â1â in succession. The bit can
be set to â0â by only writing â0â.
Bit 2 is the CPU Rewrite Mode Entry Flag. This flag indicates â1â in
CPU rewrite mode, so that reading this flag can check whether
CPU rewrite mode has been entered or not.
Bit 3 is the flash memory reset bit used to reset the control circuit
of internal flash memory. This bit is used when exiting CPU rewrite
mode and when flash memory access has failed. When the CPU
Rewrite Mode Select Bit is â1â, setting â1â for this bit resets the
control circuit. To set this bit to â1â, it is necessary to write â0â and
then write â1â in succession. To release the reset, it is necessary
to set this bit to â0â.
Bit 4 is the User Area/Boot Area Select Bit. When this bit is set to
â1â, Boot ROM area is accessed, and CPU rewrite mode in Boot
ROM area is available. In Boot mode, this bit is set to â1â auto-
matically. Reprogramming of this bit must be in a memory other
than internal flash memory.
Figure 148 shows a flowchart for setting/releasing CPU rewrite
mode.
b7
b0
Flash memory control register (address 0FFE16)
FMCR (Note 1)
RY/BY status flag
0: Busy (being written or erased)
1: Ready
CPU rewrite mode select bit (Note 2)
0: Normal mode (Software commands invalid)
1: CPU rewrite mode (Software commands acceptable)
CPU rewrite mode entry flag
0: Normal mode (Software commands invalid)
1: CPU rewrite mode
Flash memory reset bit (Note 3)
0: Normal operation
1: Reset
User area / Boot area select bit (Note 4)
0: User ROM area accessed
1: Boot ROM area accessed
Reserved bits (indefinite at read/ â0â at write)
Notes 1: The contents of flash memory control register are âXXX00001â just after reset release.
2: For this bit to be set to â1â, the user needs to write â0â and then â1â to it in succession. If it is not
this procedure, this bit will not be set to â1â. Additionally, it is required to ensure that no interrupt
will be generated during that interval.
Use the control program in the area except the built-in flash memory for write to this bit.
3: This bit is valid when the CPU rewrite mode select bit is â1â. Set this bit 3 to â0â subsequently after
setting bit 3 to â1â.
4: Use the control program in the area except the built-in flash memory for write to this bit.
Fig. 147 Structure of flash memory control register
Rev.3.00 Oct 15, 2006 page 101 of 147
REJ03B0193-0300
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