38K2 Datasheet, PDF (55/151 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K2 Group
(6) Endpoint 11
b7
b0
0
0
0 0 0 EP11 set register (EP11CFG) [address 001916]
Bit symbol
Bit name
b2:b0
Not used
SQCL11 Sequence toggle bit clear bit
b4
DIR11
b6
TYP11
Not used
Transfer direction bit
Not used
Transfer type bite
Function
At reset
RW
H/W S/W
Write “0” when writing.
– – OO
“0” is read when reading.
0 : Toggle bit clear disabled
0–
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
“0” is always read when reading.
Write “0” when writing.
– – OO
“0” is read when reading.
0 : IN transfer disabled
0 – OO
1 : IN (Data is transmitted to the host.)
Write “0” when writing.
– – OO
“0” is read when reading.
0 : Transfer disabled
0 – OO
1 : Interrupt transfer
–: State remaining
Fig. 81 Structure of EP11 set register
b7
0 00 0 0 0
b0
EP11 control register 1 (EP11CON1) [address 001A16]
Bit symbol
Bit name
PID11
[1:0]
Response PID bit
b7:b2
Not used
Function
b1 b0
0 0 : NAK
0 1 : Automatic response (NAK, DATA0, DATA1)
1 X : STALL
Write “0” when writing.
“0” is read when reading.
At reset _{R W}
H/W S/W
0 – OO
– – OO
–: State remaining
Fig. 82 Structure of EP11 control register 1
b7
b0
0 0 0 00 0 0
EP11 control register 2 (EP11CON2) [address 001B16]
Bit symbol
Bit name
B0VAL11 Buffer 0 status bit
b7:b1
Not used
Function
At reset _{R W}
H/W S/W
This bit set to “1” shows the transmitting data is in a set 0 – O O
state (SIE is possible to read).
Write “0” when writing.
– – OO
“0” is read when reading.
–: State remaining
Fig. 83 Structure of EP11 control register 2
Rev.3.00 Oct 15, 2006 page 55 of 147
REJ03B0193-0300