38K2 Datasheet, PDF (85/151 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K2 Group
(5) Memory Channel Receiving Operation (3)-
Burst Mode (Terminal Count)
Memory channel receiving operation (3) is shown bellow.
Address ExA0
Chip select ExCS
DMA acknowledge
ExDACK
Terminal count ExTC
Write ExWR
A0 = “x”
CS = “1”
Dack = “0”
Data DQ0 to DQ7
Internal clock φ
DMA request
ExDREQ
mWR detection
#0
Mch_req
mWR detection
Receive buffer RxBuf
mTC detection
TC synchronizing
TC end
Operation enabled
Main sequencer
0
1
2
Memory channel operation
end interrupt
Internal memory access
➀’
A0 = “x”
CS = “1”
Dack = “0”
➀’
TC
#1
➁’
➀
➀
#0
3
req
#1
➁’ ➁’
(5)
➁’ ➁’
Memory address
Counter end
Burst end
010016
010116
010216
Acknowledgment of
internal memory access
ack
ack
<Initial setting>
External I/O configuration register
Memory channel operation mode register
Memory address counter
End address register
Set as necessary.
MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)
Burst (burst) = “1” (Burst mode)
(Example) 010016
(Example) 010716
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
➀ When a rise of TC is detected, negation of the memory channel request which synchronized with a rise of φ is made.
➁ When the write operation to the end address has been completed, the memory channel operation end interrupt is generated.
Fig. 126 Memory channel receiving operation (3)
➁
➁
5
➁
Rev.3.00 Oct 15, 2006 page 85 of 147
REJ03B0193-0300