38K2 Datasheet, PDF (35/151 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K2 Group
b7
b0
USB interrupt source register (USBIREQ) [address 001716]
Bit symbol
Bit name
EP00
USB function/Endpoint 0
interrupt bit
EP01
USB function/Endpoint 1
interrupt bit
EP02
USB function/Endpoint 2
interrupt bit
EP03
USB function/Endpoint 3
interrupt bit
EP10
USB HUB/Endpoint 0 interrupt
bit
EP11
USB HUB/Endpoint 1 interrupt
bit
SUS
Suspend interrupt bit
RSM
Resume interrupt bit
Function
At reset _{R W}
H/W S/W
This bit is set to “1” when any one of EP00 interrupt 0 0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP00 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP01 interrupt 0 0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP01 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP02 interrupt 0 0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP02 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP03 interrupt 0 0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP03 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP10 interrupt 0 0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP10 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP11 interrupt 0 0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP11 interrupt
source register to “0016”.
Writing to this bit causes no state change.
0 : No interrupt request issued
0 0 OO
1 : Interrupt request issued
This bit is set to “1” when detecting 3 ms or more of J-
state, using USB clock (fUSB) at 48 MHz.
“0” can be set by software, but “1” cannot be set.
This bit is set to “1” when the USB bus state changes 0 0 O ✕
from J-state to K-state or SE0 in the resume interrupt
enable bit = “1”. It is also “1” in the condition of internal
clock stopped.
This bit is cleared to “0” by clearing the resume
interrupt enable bit.
Writing to this bit causes no state change.
Fig.38 Structure of USB interrupt source register
Rev.3.00 Oct 15, 2006 page 35 of 147
REJ03B0193-0300