38K2 Datasheet, PDF (106/151 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K2 Group
Status Register (SRD)
The status register shows the operating status of the flash
memory and whether erase operations and programs ended suc-
cessfully or in error. It can be read in the following ways:
(1) By reading an arbitrary address from the User ROM area after
writing the read status register command (7016)
(2) By reading an arbitrary address from the User ROM area in the
period from when the program starts or erase operation starts
to when the read array command (FF16) is input.
Also, the status register can be cleared by writing the clear status
register command (5016).
After reset, the status register is set to “8016”.
Table 11 shows the status register. Each bit in this register is ex-
plained below.
•Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory. This bit is set to “0” (busy) during write or erase operation
and is set to “1” when these operations ends.
After power-on, the sequencer status is set to “1” (ready).
•Erase status (SR5)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is set to “0”.
•Program status (SR4)
The program status indicates the operating status of write opera-
tion. When a write error occurs, it is set to “1”.
The program status is set to “0” when it is cleared.
If “1” is written for any of the SR5 and SR4 bits, the program,
erase all blocks, and block erase commands are not accepted.
Before executing these commands, execute the clear status regis-
ter command (5016) and clear the status register.
Table 11 Definition of each bit in status register
Each bit of
SRD0 bits
Status name
SR7 (bit7)
Sequencer status
SR6 (bit6)
Reserved
SR5 (bit5)
Erase status
SR4 (bit4)
Program status
SR3 (bit3)
Reserved
SR2 (bit2)
Reserved
SR1 (bit1)
Reserved
SR0 (bit0)
Reserved
Definition
“1”
“0”
Ready
Busy
-
-
Terminated in error
Terminated normally
Terminated in error
Terminated normally
-
-
-
-
-
-
-
-
Rev.3.00 Oct 15, 2006 page 106 of 147
REJ03B0193-0300