38K2 Datasheet, PDF (58/151 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K2 Group
HUB Function Control Circuit Block Diagram
The HUB function control circuit, as show in the diagram below,
consists of the following blocks.
(1) HUB repeater block
(2) Down-port control block
(3) CPU interface block (CIF)
HUB Function Control Circuit
HUB repeater block
D0+
D0-
Down-port control block
USB down-port 1
transceiver
D1+ D1-
USB Down-port 2
transceiver
D2+ D2-
Fig. 88 HUB function control circuit block diagram
(1) HUB repeater block
The HUB repeater block, consisting of the circuits listed below,
processes the HUB repeater function sequence. The HUB re-
peater is ready for operation after enabling the USB module
(USBE = “1”).
•Repeater circuit (detects SOP/EOP signal)
•Frame-time circuit (synchronizes to SOF signal and manages
frames in 1 ms)
•Receiver circuit (manages up-port states)
•Transmitter circuit (controls up-port outputs)
(2) Down-port control block
The down-port control block, consisting of the circuits listed below,
performs down-port controls under supervision of the HUB re-
peater state operation.
•Down-port sequencer circuit
•Down-port state change detect circuit
(3) CPU interface block (CIF)
The CPU interface block performs the following processes.
•Control of repeater/down-port states through registers.
•Generates interrupt signal
•Controls internal bus interface
Rev.3.00 Oct 15, 2006 page 58 of 147
REJ03B0193-0300