38K2 Datasheet, PDF (104/151 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K2 Group
Software Commands
Table 10 lists the software commands.
After setting the CPU Rewrite Mode Select Bit to “1”, write a soft-
ware command to specify an erase or program operation.
Each software command is explained below.
____
During the program movement, The RY/BY Status Flag of flash
memory control register is set to “0”. When the program com-
pletes, it becomes “1”.
At program end, program results can be checked by reading the
status register.
qRead Array Command (FF16)
The read array mode is entered by writing the command code
“FF16” in the first bus cycle. When an address to be read is input in
one of the bus cycles that follow, the contents of the specified ad-
dress are read out at the data bus (D0 to D7).
The read array mode is retained intact until another command is
written.
qRead Status Register Command (7016)
When the command code “7016” is written in the first bus cycle,
the contents of the status register are read out at the data bus (D0
to D7) by a read in the second bus cycle.
The status register is explained in the next section.
Start
Write 4016
Write ^{Write address}
Write data
Status register
read
qClear Status Register Command (5016)
This command is used to clear the bits SR4 and SR5 of the status
register after they have been set. These bits indicate that opera-
tion has ended in an error. To use this command, write the
command code “5016” in the first bus cycle.
SR7 = 1 ?
or
NO
RY/BY = 1 ?
YES
qProgram Command (4016)
SR4 = 0 ?
NO
Program operation starts when the command code “4016” is writ-
ten in the first bus cycle. Then, if the address and data to program
are written in the 2nd bus cycle, the control circuit of flash memory
(data programming and verification) will start a program.
Whether the write operation is completed can be confirmed by
_____
reading the status register or the RY/BY Status Flag. When the
YES
Program
completed
program starts, the read status register mode is entered automati-
cally and the contents of the status register is read at the data bus
(DB0 to DB7). The status register bit 7 (SR7) is set to “0” at the
Fig. 149 Program flowchart
same time the write operation starts and is returned to “1” upon
completion of the write operation. In this case, the read status reg-
ister mode remains active until the read array command (FF16) is
written.
Table 10 List of software commands (CPU rewrite mode)
Program
error
Command
Read array
Read status register
Clear status register
Cycle number
1
2
1
Mode
Write
Write
Write
First bus cycle
Address
Data
(D0 to D7)
X ^{(Note 4)}
FF16
X
7016
X
5016
Program
2
Write
X
4016
Erase all blocks
2
Write
X
2016
Block erase
2
Write
X
2016
Notes 1: SRD = Status Register Data
2: WA = Write Address, WD = Write Data
3: BA = Block Address to be erased (Input the maximum address of each block.)
4: X denotes a given address in the User ROM area .
Second bus cycle
Mode Address
Data
(D0 to D7)
Read
X
SRD ^{(Note 1)}
Write
Write
Write
WA ^{(Note 2)} WD ^{(Note 2)}
X
2016
BA ^{(Note 3)}
D016
Rev.3.00 Oct 15, 2006 page 104 of 147
REJ03B0193-0300