38K2 Datasheet, PDF (75/151 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K2 Group
EXB Register List
The EXB register list is shown below.
Address
Register Name
SYMBOL
bit7
bit6
003016
003116
EXB interrupt source enable register
EXB interrupt source register
EXBICON
EXBIREQ
003316
003416
003516
EXB index register
Register window 1 (low)
Register window 2 (high)
EXBINDEX
0
0
EXBREG1
EXBREG2
Fig. 107 EXB related registers (1)
•EXB interrupt source enable register
This register enables/disables access from an external bus and an
internal interrupt.
•EXB interrupt source register
This register indicates the state of CPU channel’s transmit/receive
buffer register and the memory channel. The same value can be
read out from the external MCU bus by using the buffer status
read select signal (A1 pin = “H”).
EXB SFR
bit5
bit4
bit3
bit2
bit1
bit0
MC_ENB
MC_STS[1:0]
TXB_ENB
TXB_EMPTY
RXB_EMB
RXB_FULL
0
0
0
LOW_WIN[7:0]
HIGH_WIN[7:0]
INDEX[2:0]
: Not used
0 : “0” fixed
•EXB index register/Register windows 1, 2
The accessible register is switched by treating addresses 003416
and 003516 as a register window depending on the value of EXB
index register at address 003316.
Index
low
high
Register Name SYMBOL
bit7
bit6
bit5
EXB SFR
bit4
bit3
bit2
bit1
bit0
0016
low External I/O configu-
ration register
high
EXBCFGL
EXBCFGH
A1_CTR
TC_CTR
INT_CTR[2:0]
DAK_CTR[1:0]
EXB_CTR
DRQ_CTR[1:0]
0116
low Transmit/Receive
buffer register
high
RXBUF/TXBUF
—
At CPU read : RXBUF[7:0]
At CPU write : TXBUF[7:0]
0216
low Memory channel ope- MCHMOD
ration mode register
high
—
BURST
MC_DIR[1:0]
0316 low Memory address
counter
MEMADL
IM_A[7:0]
high
MEMADH
0
0
0
0
0
IM_A[10:8]
0416 low End address
register
ENDADL
END_A[7:0]
high
ENDADH
0
0
0
0
0
END_A[10:8]
Fig. 108 EXB related registers (2)
•External I/O configuration register
This register selects the function of each pin.
•Transmit/Receive buffer register
This register consists of the receive buffer register (RXBUF) and
the transmit buffer register (TXBUF)
•Memory channel operation mode register
This register sets the operation mode of the memory channel.
: Not used
0 : “0” fixed
•Memory address counter
This is a counter to set the beginning address which FIFO ac-
cesses. This register is increased by access from the external
MCU bus.
•End address register
This register is to set the end address which FIFO accesses.
Rev.3.00 Oct 15, 2006 page 75 of 147
REJ03B0193-0300