38K2 Datasheet, PDF (90/151 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K2 Group
A/D CONVERTER
The functional blocks of the A/D converter are described below.
[AD Conversion Register 1, 2 (AD1, AD2)]
003716, 003816
The AD conversion register is a read-only register that stores the
result of an A/D conversion. When reading this register during an
A/D conversion, the previous conversion result is read.
Bit 7 of the AD conversion register 2 must be set to “0”. Not only
10-bit reading but also only high-order 8-bit reading of conversion
result can be performed by selecting the reading procedure of the
AD conversion registers 1, 2 after A/D conversion is completed (in
Figure 133).
The 8-bit reading inclined to MSB is performed when reading the
AD converter register 1 after A/D conversion is started or reset;
and when the AD converter register 1 is read after reading the AD
converter register 2, the 8-bit reading inclined to LSB is per-
formed.
[AD Control Register (ADCON)] 003616
The AD control register controls the A/D conversion process. Bits
0 to 2 select a specific analog input pin. Bit 3 signals the comple-
tion of an A/D conversion. The value of this bit remains at “0”
during an A/D conversion, and changes to “1” when an A/D con-
version ends. Writing “0” to this bit starts the A/D conversion.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
VREF and AVSS into 1024, and that outputs the comparison volt-
age.
The A/D converter successively compares the comparison voltage
Vref in each mode, dividing the VREF voltage (see below), with the
input voltage.
• 10-bit reading
Vref
=
VREF
1024
✕ n (n = 0–1023)
• 8-bit reading
Vref = ^VREF ✕ n (n = 0–255)
256
Channel Selector
The channel selector selects one of the input ports P17/AN7–P10/
AN0.
Comparator and Control Circuit
The comparator and control circuit compares an analog input volt-
age with the comparison voltage, and then stores the result in the
AD conversion registers 1, 2. When an A/D conversion is com-
pleted, the control circuit sets the AD conversion completion bit
and the AD interrupt request bit to “1”.
Note that because the comparator consists of a capacitor cou-
pling, set f(system clock) to 500 kHz or more during an A/D
conversion.
b7
b0 _{AD control register}
(ADCON : address 003616)
Analog input pin selection bits
0 0 0 : P10/DQ0/AN0
0 0 1 : P11/DQ1/AN1
0 1 0 : P12/DQ2/AN2
0 1 1 : P13/DQ3/AN3
1 0 0 : P14/DQ4/AN4
1 0 1 : P15/DQ5/AN5
1 1 0 : P16/DQ6/AN6
1 1 1 : P17/DQ7/AN7
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Not used (indefinite at read)
(These bits are write disabled bits.)
Fig. 132 Structure of AD control register
10-bit reading
(Read address 003816 before 003716)
b7
(address 003816)
0
b0
b9 b8
(address 003716)
b7
b0
b7 b6 b5 b4 b3 b2 b1 b0
Note : Bits 2 to 7 of address 003816 become “0”
at reading.
8-bit reading
(Read only address 003716)
b7
b0
(address 003716)
b9 b8 b7 b6 b5 b4 b3 b2
Fig. 133 10-bit/8-bit reading
Rev.3.00 Oct 15, 2006 page 90 of 147
REJ03B0193-0300