38K2 Datasheet, PDF (48/151 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

38K2 Group
(4) Endpoint 03
b7
b0
EP03 set register (EP03CFG) [address 001916]
Bit symbol
BSIZ03
[1:0]
DBLB03
SQCL03
ITMD03
DIR03
TYP03
[1:0]
Bit name
Function
At reset _{R W}
H/W S/W
Double buffer beginning address set In double buffer mode set the beginning address of buffer 1 0 – O O
bit
area, using a relative value for the beginning address of
buffer 0.
b1b0
0 0 = 8 bytes
0 1 = 16 bytes
1 0 = 64 bytes
1 1 = 128 bytes
Buffer mode select bit
0 : Single buffer mode
0 – OO
1 : Double buffer mode
Sequence toggle bit clear bit 0 : Toggle bit clear disabled
0 – OO
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
“0” is always read when reading.
Interrupt toggle mode select bit 0 : Normal mode
0 – OO
1 : Continuous toggle mode (valid at Interrupt IN transfer)
Transfer direction bit
0 : OUT (Data is received from the host.)
0 – OO
1 : IN (Data is transmitted to the host.)
Transfer type bit
b7b6
0 – OO
0 0 : Transfer disabled
0 1 : Bulk transfer
1 0 : Interrupt transfer
1 1 : Isochronous transfer
–: State remaining
Fig. 65 Structure of EP03 set register
b7
0 00 0 0 0
b0
EP03 control register 1 (EP03CON1) [address 001A16]
Bit symbol
Bit name
PID03
[1:0]
Response PID bit
b7:b2
Not used
Function
b1 b0
0 0 : NAK
0 1 : Automatic response (ACK, NAK, DATA0, DATA1)
1 X : STALL
At occurrence of over-max. packet size :
B1 is set to “1” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
H/W S/W
0–
––
RW
OO
OO
–: State remaining
Fig. 66 Structure of EP03 control register 1
Rev.3.00 Oct 15, 2006 page 48 of 147
REJ03B0193-0300